DDR5 RAM: Specification update published by JEDEC

After the JEDEC Solid State Technology Association had finally specified the DDR5 SDRAM standard, which is about to be introduced into the mass market, the publication of an update with the designation "JESD79-5A" has now been announced. The updated version is said to contain features that " improve the reliability and performance in a wide range of applications for client systems and high-performance servers ". The complete specification for the JESD79-5A update is provided as a chargeable downloadable PDF file from the JEDEC website. More error correction

The new functions, therefore, include above all points with which " the demand of the industry for improved system reliability is to be met ", including support for corrections for limited errors (bounded fault error correction), undo and lock for soft post-package repair ( sPPR), Memory Built-In Self-Test Post Package Repair (MBIST and mPPR), Adaptive RFM and an MR4 extension. Further update

JESD79-5A also extends the timing definition and transfer speed of DDR5 up to 6,400 MT / s for DRAM core timings and 5,600 MT / s for IO-AC timings. The nomenclature for core timing parameters and their respective definitions have also been revised to closely align them with the upcoming standard called "JEDEC JESD400-5 DDR5 Serial Presence Detect (SPD) Contents V1.0", it says. Statement on the DDR5 update

" The fact that this update for DDR5 will be released so soon after the market launch in July 2020 underscores JEDEC's ongoing commitment to continuous improvement and represents a joint effort by all member companies involved to offer the industry better service ", it says in the announcement by Mian Quddus, the chairman of JEDEC. In addition, the press release on the update also has positive voices on the new RAM standard from industry representatives, including AMD, Intel, Micron, Samsung and SK Hynix.

By: Olivia J. - Zexron